Cypress Semiconductor /psoc63 /FLASHC /BIST_CTL

This field specifies how the data check should be performed after reading the data from Flash memory. ‘0’: Read the Flash and compare the output to BIST_DATA (R0). ‘1’: Read the Flash and compare the output to the binary complement of BIST_DATA (R1). ‘2’: Read the Flash and compare with BIST_DATA[] and compliment of BIST_DATA alternately (R01). The expected data of the first read is BIST_DATA, expected data of the second read is binary compliment of BIST_DATA, third read expected data is BIST_DATA, fourth read expected data is binary compliment of BIST_DATA and so on.

Specifies direction in which Flash BIST steps through addresses: '‘0’: BIST steps through the Flash from the maximum row and column addresses (as specified by a design time configurtion parameter when ADDR_START_ENABLED is ‘0’ and as specified by BIST_ADDR_START when ADDR_START_ENABLED is ‘1’) to the minimum row and column addresses. ‘1’: BIST steps through the Flash from the minimum row and column addresses (‘0’ when ADDR_START_ENABLED is ‘0’ and as specified by BIST_ADDR_START when ADDR_START_ENABLED is ‘1’) to the maximum row and column addresses.

Specifies how the Flash BIST addresses are generated: ‘0’: Column address is incremented/decremented till it reaches its maximum/minimum value. Once it reach its maximum/minimum value, it is set to its mimimum/maximum value and only then is the row address incremented/decremented. ‘1’: Row address is incremented/decremented till it reaches its maximum/minimum value. Once it reach its maximum/minimum value, it is set to its mimimum/maximum value and only then is the column address incremented/decremented.

Specifies Flash BIST start addresses: ‘0’: Row and column addresses start with their maximum/minimum values. ‘1’: Row and column addresses start with their values as specified by BIST_ADDR_START.

This feature is supported only for simple increment/decrement patterns. It is not supported with address compliment pattern (BIST_CTL.ADDR_COMPLIMENT_ENABLED) or address pattern which increments/decrements both row address and column address (BIST_CTL.INCR_DECR_BOTH) for every read.

Specifies to generate address compliment patterns. ‘0’: Generate normal increment/decrement patterns. ‘1’: Generate address patterns which interleaves compliment of previous address in between. Example: The following is an exaple pattern, With UP=1 and ROW_FIRST =0 00_00 11_11 00_01 11_10 00_10 11_01 …

Specifies to generate patterns where both column address and row address are incremented/decremented simultaneously. ‘0’: Generate normal increment/decrement patterns. ‘1’: Generate address patterns with both row and column address changing. Example: With UP = 1 and ROW_FIRST = 0 00_00 01_01 10_10 11_11 00_01 01_10 10_11 11_00 00_10 …

Specifies the BIST to continue indefinitely, regardless of occurrence of errors or not. ‘0’: BIST controller doesn’t stop on the data failures, it continues regardless of the errors. ‘1’: BIST controller stops on when the first data failure is encounted.